Currently, the present MOS varactors have a limited tuning range which may also overlap positive and negative biases in order to encompass a complete tuning range as required by the circuit they are used in.
Past implementations to improve the tuneability of a varactor have utilized separate n and p type gates wired in parallel. This approach increases the total required area and therefore is not an optimum solution.
U.S. Pat. No. 6,667,539, to E. Alder, provides for a MOS varactor circuit having a pair of serially-connected varactors whose junctions are connected via a tap of a resistor to a resistor which is connected to adjacent terminals.
Solutions that provide for MOS varactors with improved tuneability without impacting area, are of great value.